diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 2db2e4b..2e77bb3 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -181,87 +181,112 @@ static inline int is_64bit_memory(u32 mask)
 	return 0;
 }
 
+static int __pci_read_base(struct pci_dev *dev, unsigned int reg,
+							struct resource *res)
+{
+	u32 l, sz;
+	u32 raw_sz;
+
+	res->name = pci_name(dev);
+	pci_read_config_dword(dev, reg, &l);
+	pci_write_config_dword(dev, reg, ~0);
+	pci_read_config_dword(dev, reg, &sz);
+	pci_write_config_dword(dev, reg, l);
+	if (!sz || sz == 0xffffffff)
+		return 0;
+	if (l == 0xffffffff)
+		l = 0;
+	raw_sz = sz;
+	if ((l & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY) {
+		sz = pci_size(l, sz, (u32)PCI_BASE_ADDRESS_MEM_MASK);
+		/*
+		 * For 64bit prefetchable memory sz could be 0, if the
+		 * real size is bigger than 4G, so we need to check
+		 * szhi for that.
+		 */
+		if (!is_64bit_memory(l) && !sz)
+			return 0;
+		res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
+		res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK;
+	} else {
+		sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
+		if (!sz)
+			return 0;
+		res->start = l & PCI_BASE_ADDRESS_IO_MASK;
+		res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK;
+	}
+	res->end = res->start + (unsigned long) sz;
+	res->flags |= pci_calc_resource_flags(l);
+	if (is_64bit_memory(l)) {
+		u32 szhi, lhi;
+		u64 sz64, l64;
+
+		pci_read_config_dword(dev, reg+4, &lhi);
+		pci_write_config_dword(dev, reg+4, ~0);
+		pci_read_config_dword(dev, reg+4, &szhi);
+		pci_write_config_dword(dev, reg+4, lhi);
+		sz64 = ((u64)szhi << 32) | raw_sz;
+		l64 = ((u64)lhi << 32) | l;
+		sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK);
+#if BITS_PER_LONG == 64
+		if (!sz64) {
+			res->start = 0;
+			res->end = 0;
+			res->flags = 0;
+			return 1;
+		}
+		res->start = l64 & PCI_BASE_ADDRESS_MEM_MASK;
+		res->end = res->start + sz64;
+#else
+		if (sz64 > 0x100000000ULL) {
+			printk(KERN_ERR "PCI: Unable to handle 64-bit "
+				"BAR for device %s\n", pci_name(dev));
+			res->start = 0;
+			res->flags = 0;
+		} else if (lhi) {
+			/* 64-bit wide address, treat as disabled */
+			pci_write_config_dword(dev, reg,
+				l & ~(u32)PCI_BASE_ADDRESS_MEM_MASK);
+			pci_write_config_dword(dev, reg+4, 0);
+			res->start = 0;
+			res->end = sz;
+		}
+#endif
+		return 1;
+	}
+	return 0;
+}
+/**
+ * pci_read_base
+ */
+int pci_read_base(struct pci_dev *dev, unsigned int reg, struct resource *res)
+{
+	struct pci_bus_region region;
+	struct resource *parent;
+
+	__pci_read_base(dev, reg, res);
+
+	region.start = res->start;
+	region.end = res->end;
+	pcibios_bus_to_resource(dev, res, &region);
+
+	parent = pci_find_parent_resource(dev, res);
+	if (!parent)
+		return -ENOENT;
+	return request_resource(parent, res);
+}
+EXPORT_SYMBOL_GPL(pci_read_base);
+
 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
 {
-	unsigned int pos, reg, next;
+	unsigned int pos, reg;
 	u32 l, sz;
 	struct resource *res;
 
-	for(pos=0; pos<howmany; pos = next) {
-		u64 l64;
-		u64 sz64;
-		u32 raw_sz;
-
-		next = pos+1;
+	for (pos = 0; pos < howmany; pos++) {
 		res = &dev->resource[pos];
-		res->name = pci_name(dev);
 		reg = PCI_BASE_ADDRESS_0 + (pos << 2);
-		pci_read_config_dword(dev, reg, &l);
-		pci_write_config_dword(dev, reg, ~0);
-		pci_read_config_dword(dev, reg, &sz);
-		pci_write_config_dword(dev, reg, l);
-		if (!sz || sz == 0xffffffff)
-			continue;
-		if (l == 0xffffffff)
-			l = 0;
-		raw_sz = sz;
-		if ((l & PCI_BASE_ADDRESS_SPACE) ==
-				PCI_BASE_ADDRESS_SPACE_MEMORY) {
-			sz = pci_size(l, sz, (u32)PCI_BASE_ADDRESS_MEM_MASK);
-			/*
-			 * For 64bit prefetchable memory sz could be 0, if the
-			 * real size is bigger than 4G, so we need to check
-			 * szhi for that.
-			 */
-			if (!is_64bit_memory(l) && !sz)
-				continue;
-			res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
-			res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK;
-		} else {
-			sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
-			if (!sz)
-				continue;
-			res->start = l & PCI_BASE_ADDRESS_IO_MASK;
-			res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK;
-		}
-		res->end = res->start + (unsigned long) sz;
-		res->flags |= pci_calc_resource_flags(l);
-		if (is_64bit_memory(l)) {
-			u32 szhi, lhi;
-
-			pci_read_config_dword(dev, reg+4, &lhi);
-			pci_write_config_dword(dev, reg+4, ~0);
-			pci_read_config_dword(dev, reg+4, &szhi);
-			pci_write_config_dword(dev, reg+4, lhi);
-			sz64 = ((u64)szhi << 32) | raw_sz;
-			l64 = ((u64)lhi << 32) | l;
-			sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK);
-			next++;
-#if BITS_PER_LONG == 64
-			if (!sz64) {
-				res->start = 0;
-				res->end = 0;
-				res->flags = 0;
-				continue;
-			}
-			res->start = l64 & PCI_BASE_ADDRESS_MEM_MASK;
-			res->end = res->start + sz64;
-#else
-			if (sz64 > 0x100000000ULL) {
-				printk(KERN_ERR "PCI: Unable to handle 64-bit "
-					"BAR for device %s\n", pci_name(dev));
-				res->start = 0;
-				res->flags = 0;
-			} else if (lhi) {
-				/* 64-bit wide address, treat as disabled */
-				pci_write_config_dword(dev, reg,
-					l & ~(u32)PCI_BASE_ADDRESS_MEM_MASK);
-				pci_write_config_dword(dev, reg+4, 0);
-				res->start = 0;
-				res->end = sz;
-			}
-#endif
-		}
+		pos += pci_read_base(dev, reg, res);
 	}
 	if (rom) {
 		dev->rom_base_reg = rom;